Recently, many CCD delay lines have been used in television receivers and other electric devices in order to delay an analog signal such as video signal. The delay line is normally supplied with an input signal while a certain input source bias voltage is applied to an input source region.
The input source bias voltage has so far been adjusted to a certain value by a variable resistor or the like provided on the outside of the delay line. Using this method of adjustment, the input source bias voltage level is subject to change according to the temperature. When the input source bias voltage level changes, the linearity of the delay line also changes. Also, adjusting the input source bias voltage to a certain value in this manner takes much time.
In order to alleviate this problem, a CCD delay line has been developed which has a bias adjusting circuit capable of automatically adjusting the input bias voltage to a certain value.
As shown in FIG. 1, a conventional CCD delay line has a first transfer region 21 (representing a first register) composed of a CCD which is formed in a semiconductor substrate (not shown) and has an input source 21a. In the first transfer region 21, signal charge is transferred. Also, second and third transfer regions 22 and 23 composed of CCDs are formed in the semiconductor substrate to constitute a bias adjusting circuit and have input sources 22a and 23a, respectively. The input source 21a of the first transfer region 21 has substantially the same structure as the input source 22a of the second transfer region 22. The first and second transfer regions 21 and 22 can carry substantially same amount of charge.
The third transfer region 23 can carry a certain portion (for example, 30%) of charge relative to the amount of charge which the first and second transfer regions 21 and 22 can carry. The third transfer region 23 is connected through the input source 23a to a DC power supply 23b. A plurality of transfer electrodes (not shown) are formed in each of the transfer regions 21, 22 and 23. The second and third transfer regions 22 and 23 have the same output structure, and have their outputs connected to a differential amplifier 24. The output of this differential amplifier is connected to the input sources 21a, 22a of the first and second transfer regions 21, 22. Moreover, a clamp circuit 25 for clamping an input signal is connected to an input gate electrode 21b of the first transfer region 21. A reference bias voltage equal to the voltage applied to the clamp circuit 25 is applied through a DC power supply E to an input gate electrode 22b of the second transfer region 22.
Upon operation of the conventional CCD delay line, the DC power supply 23b is kept at a proper voltage under which the maximum amount of charge are always transferred through the third transfer region 23. The output voltage from the third transfer region 23 is supplied to the differential amplifier 24, where it is compared with the voltage applied from the second transfer region 22. The voltage difference from the differential amplifier 24 is fed back to the input source 22a of the second transfer region 22 and to the input source 21a of the first transfer region 21. In addition, a reference bias voltage equal to the input bias voltage to the clamp circuit 25 is applied to the input gate electrode 22b of the second transfer region 22. Thus, the input source 22a supplies charge into the second transfer region 22. The output voltage from the second transfer region 22 is fed to the differential amplifier 24. Then, this operation is repeated.
In the steady state, if the maximum amount of charge which the third transfer region 23 can carry is 30% of the maximum amount of charge which the second transfer region 22 can carry, the second transfer region 22 is operating under the bias condition of 30% of its maximum amount of charge to be transferred. Since the first transfer region 21 has the same input structure and can carry the same maximum amount of charge as the second transfer region 22, the first transfer region 21 can be operated under the bias condition of 30% of its maximum amount of charge to be transferred.
The conventional CCD delay line, however, has the following problem. That is, the manufacturing process for this CCD delay line sometimes needs to change the operating point, or bias condition of the bias adjusting circuit in order to improve the characteristics. In this case, since the change of the operating point has so far been made by changing the maximum amount of charge which the third transfer region 23 can carry, the improvement cannot be confirmed in a short period of time. In other words, in order to change the maximum amount of charge which the third transfer region 23 can carry, the transfer channel width of the channel region must be changed, and for this purpose it is necessary to change the must pattern in the exposure process. Since the process for forming the channel region is performed at the initial stage of the manufacturing process, a long period of time will be taken until it is confirmed whether the operating point has been correctly changed after the change of mask pattern.